In surface micromechanics, there is a possibility, when manufacturing integrated sensor elements, to produce cavities for such devices along with other electrical devices in an integrated circuit. Thus, the process steps for manufacturing the micromechanics components (micromechanics process steps) are partly of considerable influence for the characteristics of the electrical devices processed. One consequence frequently resulting is a limitation in the degrees of freedom in the process management for manufacturing and sealing cavities in these devices. The result is that disadvantages in the characteristics of the micromechanical devices partly have to be put up with. An example of such a limitation or a disadvantage in the characteristics of such a micromechanical device is that it might be of particular importance, in particular in modern processes and devices, for the doping profiles provided not to be shifted.
At present, two-chip solutions are predominantly used to solve these problems, one chip containing the micromechanical structures and a second chip containing evaluating electronics for processing the signals obtained from the first chip. The two devices are processed separately. A mutual process influencing in the form of process influences of the respective other manufacturing processes can be avoided here. The disadvantage of this solution, however, is considerable additional cost resulting from the separate process management and the separate chips. In addition, additional package expenditure results from the separate processing of the two chips, which increases the setup space of the finished device on the one hand and the manufacturing cost on the other hand. Furthermore, certain applications which are, for example, dependent on evaluating particularly small signals cannot be realized by this concept since the respective signals, for example, must be transported via bond wires via which it is particularly easy for disturbance signals to couple in the sensor.
Another solution will be described and discussed in greater detail referring to the schematic setup shown in FIG. 2 and the scanning electron microscope image shown in FIG. 3. The cavity structures here are processed after manufacturing the electrical devices. Mutual process influences in this case result in partly complicated readjusting of the electronical devices.
A cavity can be exposed by etching by a plate provided with holes which may, for example, consist of polysilicon (poly Si), silicon oxide (Si oxide) or silicon nitrite (Si nitrite). FIG. 2a shows this intermediate state of an integrated sensor element in a schematic manner. A sacrificial layer 810 which in the finished device acts as a spacing for the membrane layer 820 which in FIG. 2a is also referred to as a lid is applied on a substrate 800. The membrane layer 820 has a plurality of holes 830. A cavity 840 has been exposed by etching through the holes 830. Thus, FIG. 2a shows a cavity 840 exposed by etching comprising a lid 820 provided with holes. Subsequently, as is shown in FIG. 2b, a sealing layer 850 is applied on the membrane layer 820 and the sacrificial layer 810, wherein the sealing layer has not completely sealed the holes 830 in the membrane layer. A highly doped silicate glass, such as, for example, borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), is frequently used as a sealing layer material. FIG. 2b is a schematic representation of the device after BPSG deposition. In a subsequent process step, the device is heated, whereupon the sealing layer 850 becomes viscous and seals the holes 830, as is schematically shown in FIG. 2c. FIG. 2c is a schematic representation of the device after BPSG reflow. Apart from the basic illustration shown in FIG. 2, FIG. 3 shows a scanning electron microscope (SEM) image of a cross-section of a corresponding device including a cavity produced in this manner. In the device shown in FIG. 3, the cavity structure has been sealed by BPSG. Reference numerals used in FIG. 2 are also used for corresponding structures of FIG. 3. This manufacturing concept is, for example, described in the patent document DE 10022266 A1.
After exposing by etching the cavity 840 through the plate provided with holes or membrane layer 820, this plate or the holes 830 of the membrane layer 820 are sealed by a highly doped silicate glass, such as, for example, PSG or BPSG. Sealing by a highly doped silicate glass is possible here since this material becomes viscous at high temperatures, in the case of BPSG usually starting at around 700° C., and behaves like a well-wetting liquid. Its surface tension compensates unevenness in the topology and seals small apertures, in the present case the holes 830, in a gas-tight manner. This process step is also referred to as “reflow”.
Highly doped silicate glass which, in principle, is suitable for sealing a cavity, however, can only be used after manufacturing the electrical devices, the so-called basic process, since the highly doped silicate glass entails a very high contamination danger for the (processed) device. Even this cavity manufacturing process, comprising the sub-step of reflow which is performed after the basic process, usually influences the integrated circuit contained on the wafer and/or the electrical devices processed so that the characteristics, such as, for example, resistances, capacitances or other electrical, mechanical, optical, acoustic or different physical quantities, thereof may be altered in an unpredictable manner, which is a considerable disadvantage of this manufacturing process.
Gas-tight sealing by depositing an undoped oxide is also possible in principle, however only under very difficult conditions, since growth lines will always form here in the deposition process. In addition, undoped oxides do not exhibit a flow behavior at high temperatures, so that apertures or holes can consequently only be sealed by relatively large layer thicknesses since a hole must grow to be sealed already during deposition. Sealing apertures or holes afterwards by reflow is not possible in this case.